1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device. More particularly, the invention relates to a method of fabricating a semiconductor device that includes a conductive layer and a high-k dielectric layer that are stacked.
2. Description of Related Art
Semiconductor devices, such as, metal oxide semiconductor field effect transistors (MOSFETs) include a gate insulating layer and a gate electrode, which are sequentially stacked on a semiconductor substrate.
Many integrated semiconductor devices are complementary metal oxide semiconductor (CMOS) devices, which include both NMOS transistors and PMOS transistors. CMOS devices generally satisfy requirements such as high operational speeds and low power consumption. To realize a simplified manufacturing process and other fabrication advantages, CMOS semiconductor devices typically use the same kind of a conductive material for the gate electrode of the NMOS transistor and the gate electrode of the PMOS transistor. The conductive material that is commonly used for the gate electrode is polycrystal silicon. A silicon oxide layer is generally used for the gate insulating layer of the semiconductor device.
The speed of semiconductor devices is generally inversely proportional to the thickness of a gate insulating layer. Thus, as the thickness of the gate insulating layer of a semiconductor device decreases, the speed of the semiconductor device generally increases. However, when the thickness of a gate insulating layer is less than a critical thickness, a current leakage problem may occur. Current leakage deteriorates the performance of semiconductor devices. In recent years, the thickness of the silicon oxide gate insulating layer has reached a critical limit. Thus, using a silicon oxide layer as a gate insulating layer may be a technical limitation. High-k dielectric layers are being actively researched as a replacement for gate oxide layers.
A semiconductor device can block leakage current even when the effective oxide thickness (EOT) of the high-k dielectric layer is less than the critical thickness of the silicon oxide layer. The EOT of the high-k dielectric layer corresponds to a thickness of a silicon oxide layer having the same capacitance as the high-k dielectric layer. Therefore, using a high-k dielectric layer as the gate insulating layer has the same effect as using a gate insulating layer that is physically larger than and electrically smaller (e.g., less capacitance) than a silicon oxide layer. Because a dielectric layer having a relatively larger thickness is used, the leakage current of the gate insulating layer can be significantly reduced.
When a high-k dielectric layer is used as the gate insulating layer, the gate insulating layer reacts with the polycrystal silicon and a silicon oxide layer is formed. The formed silicon oxide layer increases the total EOT of the gate insulating layer. When a high-k dielectric layer is used as the gate insulating layer, the fixed charge included in the high-k dielectric layer reduces the mobility of carriers in a channel region under the gate electrode.